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ISL54057
Data Sheet September 29, 2006 FN6379.0
Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer
The Intersil ISL54057 device contains precision, bidirectional, analog switches configured as a differential 4-channel multiplexer/demultiplexer, designed to operate from a single +1.6V to +3.6V supply. The devices have an inhibit pin to simultaneously open all signal paths. ON resistance is 0.41 with a +3V supply and 0.61 with a single +1.8V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 4nA max at +25C or 35nA max at +85C with a +3.3V supply. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL54057 is a differential 4 to 1 multiplexer device that is offered in a 16 Ld 2.6x1.8x0.5mm TQFN package. Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE ISL54057 Configuration 3V RON 3V tON/tOFF 1.8V RON 1.8V tON/tOFF Packages Diff 4:1 Mux 0.41 27ns/18ns 0.61 34ns/26ns 16 Ld 2.6x1.8x0.5mm TQFN
Features
* Pb-Free Plus Anneal Available (RoHS Compliant) * ON Resistance (RON) - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.41 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.61 * RON Matching Between Channels. . . . . . . . . . . . . . . . 0.09 * RON Flatness Across Signal Range . . . . . . . . . . . . . . 0.07 * Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V * Low Power Consumption (PD). . . . . . . . . . . . . . . . . <0.18W * Fast Switching Action (VS = +3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18ns * Break-Before-Make * High Current Handling Capacity (300mA Continuous) * Available in 16 Ld 2.6x1.8x0.5mm TQFN * 1.8V CMOS-Logic Compatible (+3V Supply)
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
Ordering Information
PART NUMBER (NOTE) ISL54057IRUZ-T PART MARKING GAB TEMP. RANGE (C) -40 to +85 PACKAGE PKG. DWG. # 16 Ld Thin QFN Tape and Reel (Pb-free) L16.2.6x1.8A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54057 Pinouts
(Note 1) ISL54057 (16 LD TQFN) TOP VIEW
COMB B1 B0 10 B3 9
12 B2 V+ A0 A2
11
13
ADD1 ADD0 GND N.C.
14
15
16
1
2
3
A3
A1
NOTE: 1. 2.6mm x 1.8mm x 0.5mm
Truth Table
ISL54057 INH 1 0 0 0 0 ADD0 X 0 0 1 1 ADD1 X 0 1 0 1 SWITCH ON NONE A0, B0 A1, B1 A2, B2 A3, B3
COMA
INH
4
Pin Descriptions
PIN V+ N.C. GND INH COMA COMB A0-A3 B0-B3 ADDx FUNCTION System Power Supply Input (1.6V to 3.6V) No Connect. Not internally connected. Ground Connection Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. Analog Switch Channel A Output Analog Switch Channel B Output Analog Switch Channel A Input Analog Switch Channel B Input Address Input Pin
NOTE: Logic "0" 0.5V. Logic "1" 1.4V, with a 3V supply. X = Don't Care.
2
5
6
7
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FN6379.0 September 29, 2006
ISL54057
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages INH, Ax, Bx, ADDx (Note 2) . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Output Voltages COMx (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . 300mA Peak Current NO or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) TQFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Maximum Junction Temperature (Plastic Package) . . . . . . +150C Maximum Storage Temperature Range. . . . . . . . . . . -65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C (Lead Tips Only)
Operating Conditions
Temperature Range ISL54057IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on Ax, Bx, COMx, ADDx, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications: 3V Supply
Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified TEST CONDITIONS TEMP (C) Full (NOTE 5) MIN 0 -4 -35 -8.5 -60 1.4 -0.5 TYP 0.43 0.09 0.07 (NOTE 5) MAX UNITS V+ 0.75 0.8 0.2 0.2 0.15 0.15 4 35 8.5 60 0.5 0.5 V nA nA nA nA V V A
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON RON Matching Between Channels, RON RON Flatness, RFLAT(ON) Ax or Bx OFF Leakage Current, IAx(OFF) or IBx(OFF) COM ON Leakage Current, ICOM(ON) Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS Break-Before-Make Time, tBBM Ax or Bx OFF Capacitance, COFF COM OFF Capacitance, COFF COM ON Capacitance, CCOM(ON)
V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V to V+ (See Figure ) V+ = 2.7V, ICOM = 100mA, VAX or VBX = Voltage at max RON, Note 6 V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V t0 V+ (Note 7) V+ = 3.3V, VCOM = 0.3V, 3V, VAX or VBX = 3V, 0.3V V+ = 3.3V, VCOM = VAX or VBX = 0.3V, 3V
25 Full 25 Full 25 Full 25 Full 25 Full Full Full
DIGITAL INPUT CHARACTERISTICS
V+ = 3.3V, VINH = VADD = 0V or V+
Full
V+ = 2.7V, VAx or VBx = 1.5V, RL = 50, CL = 35pF (See Figure 1) V+ = 2.7V, VAx or VBx = 1.5V, RL = 50, CL = 35pF, See Figure 1 V+ = 2.7V, VAX or VBX = 1.5V, RL = 50, CL = 35pF (See Figure 1) V+ = 3.3V, VAX or VBX = 1.5V, RL = 50, CL = 35pF (See Figure 2) f = 1MHz, VAX or VBX = VCOM = 0V (See Figure ) f = 1MHz, VAX or VBX = VCOM = 0V (See Figure 6) f = 1MHz, VAX or VBX = VCOM = 0V (See Figure 6)
25 Full 25 Full 25 Full 25 Full 25 25 25
-
27 37 18 28 29 40 4 1 44 149 201
-
ns ns ns ns ns ns ns ns pF pF pF
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FN6379.0 September 29, 2006
ISL54057
Electrical Specifications: 3V Supply
Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified (Continued) TEST CONDITIONS RL = 50, CL = 35pF, f = 100kHz (See Figures 3 and 5) TEMP (C) 25 25 Full V+ = 3.3V, VINH, VADD = 0V or V+, Switch On or Off 25 Full NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. RON matching between channels is calculated by subtracting the channel with the highest max RON value from the channel with lowest max RON value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. 9. Between any two switches. (NOTE 5) MIN 1.6 TYP 65 -100 (NOTE 5) MAX UNITS 3.6 0.05 1.1 dB dB V A A
PARAMETER OFF Isolation Crosstalk, Note 9 Power Supply Range Positive Supply Current, I+
POWER SUPPLY CHARACTERISTICS
Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 4, 8),
Unless Otherwise Specified TEST CONDITIONS PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON RON Matching Between Channels, RON) RON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V (See Figure 4) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V (Note 6) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 0V, 0.9V, 1.6V (Note 7) Full 25 Full 25 Full 25 Full Full Full V+ = 1.8V, VINH, VADD = 0V or V+ Full 0 1 -0.5 0.61 0.11 0.12 0.19 0.19 V+ 0.85 0.9 0.4 0.5 V V V A TEMP (C) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS Break-Before-Make Time, tBBM V+ = 1.8V, VAx or VBx = 1.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 1.8V, VAx or VBx = 1.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 1.8V, VAX or VBX = 1.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 1.8V, VAX or VBX = 1.0V, RL = 50, CL = 35pF (See Figure 2A) 25 Full 25 Full 25 Full 25 34 45 26 37 35 46 9 ns ns ns ns ns ns ns
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FN6379.0 September 29, 2006
ISL54057 Test Circuits and Waveforms
C V+ LOGIC INPUT 50% 0V tON tr < 5ns tf < 5ns V+ A0, B0 A1,A2,B1, B2,A3,B3 INH 90% LOGIC INPUT COMA COMB VOUT V+ C
VA0, VB0 SWITCH OUTPUT
90%
VOUT
GND ADD0-1
0V tOFF
RL 50
CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT
FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS
V+ LOGIC INPUT 50% 0V tTRANS V+ VA0, VB0 SWITCH OUTPUT VA3, VB3 tTRANS 10%
0V
tr < 5ns tf < 5ns C
V+
C
A0, B0 A1,A2,B1, B2,A3,B3 ADD0-1 GND
COMA, COMB
VOUT
VOUT
90%
INH
LOGIC INPUT
RL 50
CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
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FN6379.0 September 29, 2006
ISL54057 Test Circuits and Waveforms (Continued)
tr < 5ns tf < 5ns V+ C C
V+ LOGIC INPUT 0V
V+ SWITCH OUTPUT VOUT 90% LOGIC INPUT
A0-A3 B0-B3 ADD0-1
COMA COMB
VOUT RL 50 CL 35pF
0V
tBBM
GND
INH
FIGURE 2A. tBBM MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 2B. tBBM TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
V+ 10nF V+
C
SIGNAL GENERATOR
Ax or Bx
RON = V1/100mA Ax or Bx VX 0V or V+ ADD1 ADD0 100mA V1 COMA or COMB GND 0V or V+ ADD1 ADD0 Channel Select INH
ANALYZER RL
COMx
Channel Select GND INH
Off-Isolation is measured between COM and "Off" NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded.
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. RON TEST CIRCUIT
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FN6379.0 September 29, 2006
ISL54057 Test Circuits and Waveforms (Continued)
V+ C V+ C 0V or V+
SIGNAL GENERATOR
Ax 0V or V+ Channel Select
50 COMA
Ax or Bx
ADD1 ADD0 Bx N.C.
IMPEDANCE ANALYZER
ADD1 ADD0 COMA or COMB GND INH Channel Select
ANALYZER RL
COMB
GND
INH
Crosstalk is measured between adjacent channels with one channel ON and the other channel OFF. Signal direction through switch is reversed and worst case values are recorded.
FIGURE 5. CROSSTALK TEST CIRCUIT
FIGURE 6. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54057 analog switch offer precise switching capability from a single 1.6V to 3.6V supply with low on-resistance (0.41) and high speed operation (tON = 27ns, tOFF = 18ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (1.6V), low power consumption (0.17W), low leakage currents (60nA max) , and the tiny TQFN package. The ultra low on-resistance and Ron flatness provide very low insertion loss and distortion to applications that require signal reproduction.
Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch. Connecting schottky diodes to the signal pins as shown in Figure 7 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 7). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail.
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR INH or ADDX Ax or Bx VCOMX
GND OPTIONAL SCHOTTKY DIODE
FIGURE 7. OVERVOLTAGE PROTECTION
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FN6379.0 September 29, 2006
ISL54057
Power-Supply Considerations
The ISL54057 construction is typical of most CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL54057 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 11 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Logic-Level Thresholds
This device is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.7V to 3.6V. At 2.7V the VIL level is about 0.54V. This is still above the 1.8V CMOS guaranteed low output maximum level of 0.5V but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 70MHz (see Figure 12).
Typical Performance Curves TA = +25C, Unless Otherwise Specified
0.8 ICOM = 100mA V+ = 1.65V 0.7 0.45 0.5 V+ = 3V ICOM = 100mA
RON ()
V+ = 1.8V 0.5
RON ()
0.6
0.4
+85C
0.35
+25C
0.4
V+ = 2.7V V+ = 3V
0.3
-40C
0.3
V+ = 3.6V 0 1 2 VCOM (V) 3 4
0.25
0
0.5
1
1.5 VCOM (V)
2
2.5
3
FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE
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FN6379.0 September 29, 2006
ISL54057 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
0.7 0.65 0.6 0.55 -40C 0.5 0.45 0.4 0.35 CROSSTALK (dB) +25C RON () 0 V+ = 1.8V ICOM = 100mA +85C V+ = 3V -10 -20 -30 450 -50 ISOLATION -60 -70 -80 -90 0 0.5 1 VCOM (V) 1.5 2 -100 1k 10k 100k 1M CROSSTALK 70 80 90 100 110 100M 500M 20 30 OFF ISOLATION (dB) 40 50 60 10
10M
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FREQUENCY (Hz)
FIGURE 11. CROSSTALK AND OFF ISOLATION
NORMALIZED GAIN (dB) V+ = 3V 0 -10 GAIN
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT:
PHASE
0 20 40 60 80 PHASE ()
228 PROCESS: Submicron CMOS
RL = 50 VIN = 0.2VP-P to 2VP-P 0.1 1 10 FREQUENCY (MHz)
100 100
FIGURE 12. FREQUENCY RESPONSE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6379.0 September 29, 2006
ISL54057 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS
6 INDEX AREA 2X 2X 0.10 C
N
E
SYMBOL A
MIN 0.45 -
NOMINAL 0.50 0.127 REF
MAX 0.55 0.05
NOTES -
12 0.10 C
A1 A3
TOP VIEW
b D
0.15 2.55 1.75
0.20 2.60 1.80 0.40 BSC
0.25 2.65 1.85
5 -
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW A
C
E e L L1 N Nd
0.35 0.45
0.40 0.50 16 4 4
0.45 0.55
2 3 3
e PIN #1 ID 12 L1 NX L NX b 5 16X 0.10 M C A B 0.05 M C BOTTOM VIEW
Ne NOTES: 0
-
12
4 Rev. 4 8/06
(DATUM B) (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
3.00 1.80 1.40 1.40
2.20
0.90 0.40 0.20 0.50 0.40 10 LAND PATTERN 0.20
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FN6379.0 September 29, 2006

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